1. Field of the Invention
The invention relates to a method for programming an automation component of an industrial automation arrangement and to a programming system for performing the method.
2. Description of the Related Art
Programmable logic controllers (PLCs) are used to automate production plants and processes. The core of a programmable logic controller is a microprocessor-based control device that is often also referred to as a Central Processing Unit (CPU). Conventional processors or processor designs (processor cores—IPs) which are known from the PC sector or the microcontroller sector are predominantly used nowadays when implementing these central assemblies (CPUs) in the programmable logic controllers. In this case, it is possible to use both individual processors and multiprocessor systems or systems having a plurality of processor cores. A hierarchically structured memory system is generally used in powerful processor systems, where the levels “closer” to the processing unit (processors), for example, the cache memory or Tightly Coupled Memory (TCM), generally have lower storage capacities, but considerably higher access speeds and lower latency times, than the general main memory (e.g., DRAM).
The technical further development of standard processors and processor cores (IPs) is substantially shaped by target markets, such as PC technology, image processing, video processing and/or data transmission (telephony, streaming). This results in both the hardware architecture and the strategies for using the cache memories or the TCM memories in the prior art being optimized with respect to the greatest possible data throughput per unit time. In other words, the average processing time for a volume of data is usually intended to be minimized. In many conventional applications in which considerable volumes of data are processed, loops or recurring subroutine sequences are used for this purpose. Here, a cache controller or a similar processing unit records the program code that is often repeatedly run through and frequently used management data, as a result of which these program and data segments are preferably held in the cache memory or TCM memory. In this case, the use of a cache memory thus only results in the optimization of the average throughput.
In contrast, in many typical applications in automation technology in which the programmable logic controllers are used, less stringent requirements are often imposed on the average processing time or a high data throughput. Instead, a stringent requirement is imposed on the reproducibility of the run time or the delay time for particular subapplications, in which case the latter should fluctuate as little as possible, i.e., they are intended to have as little “jitter” as possible. Examples thereof are motion control applications, hydraulic regulation systems, converter controllers in power electronics and the response to asynchronous events in fast-running machines and applications. Here, the TCM memory is generally deliberately used for the reproducible execution of code or for the reproducible access to data. However, the use of a TCM memory requires exact knowledge of the hardware architecture and the manual creation of special locating rules for the code and data parts.
Therefore, the conventional methods for the programmable logic controllers and the applications implemented using the latter are either less suitable (cache memory) or require a large outlay and in-depth knowledge of the hardware used in each case (TCM memory) for their implementation.
The achievable performance in the microprocessor system is highly dependent on whether the code to be processed and the associated data are already in the fast main memory “close to the core”, for example, the cache memory or the TCM memory, or are still in the comparatively slow normal main memory (usually DRAM). An entire program, i.e., an automation program, is generally larger than the fast special main memory (cache memory, TCM memory) available and the previous program flow determines which parts of the automation program and which parts of the data are in the special main memory and which parts are not. As a result, the temporal behavior of the application in general and the execution time and response time of particular functions in particular can hardly be predicted and moreover fluctuate.
This negative effect is intensified by virtue of the fact that the “jitter-critical” tasks often have a highly linear character and therefore generally do not have any local loops that are frequently run through and are preferably held by cache management devices in the special fast main memory. For PLC tasks with stringent requirements imposed on the reproducibility (for example, regulation, clock generation or response to process alarms), this fluctuating processing speed that cannot be predicted is problematic on account of “cache hit” or “cache miss” and the “jitter” occurring in this connection. Infringements of temporal requirements generally result in disruptions in the application and thus in a process or sequence to be controlled. As a result, the program run time occurring in the “worst-case” scenario, i.e., in the case of a “cache miss”, must be used as a basis for dimensioning, which results in considerable performance losses even if the average values might be considerably better. It is also difficult for the user to determine the execution time for this “worst-case” scenario since the run times of a task are severely influenced by the temporal sequences in the other tasks, which relates both to an interruption in an important task and to the “past history” of the occupancy of a cache memory and the like.